Hello Ikalogic team,
We are currently integrating the SP1000G into a test bench where we acquire data from a high‑speed ADC using multiple digital inputs. After the latest firmware updates (which significantly improved performance—thank you for that), we were finally able to push the system closer to our intended use case. However, we have identified an issue that makes the setup unviable for our application.
Use case
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~22 digital channels
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ADC operating at 50 MSPS per channel
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Effective sampling requirement: 250 MHz
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Required inter‑channel coherence: < 0.02 µs
Observed problem
We observe a channel‑to‑channel variation in the decision (threshold) voltage, which results in timing skew between channels, even when all channels are driven by the same analog signal.
With a simple test setup (same 1 kHz waveform applied to multiple channels), one channel (for example, channel B):
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Consistently rises later
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And falls earlier
than the other channels.
This behavior is repeatable and can only be mitigated by manually adjusting the decision level for that specific channel, strongly suggesting an inherent per‑channel decision‑level offset rather than a signal integrity issue.
Annexed images (to be added to this ticket) illustrate this behavior clearly, showing:
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Multiple channels receiving the same input signal
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A visible and consistent timing offset between channels
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The effect of manually adjusting the reference/decision level to compensate for the mismatch
Impact
Given the ADC speed (~50 MSPS), these decision‑level differences translate directly into inter‑channel timing errors, breaking channel coherence and preventing accurate multi‑channel signal reconstruction.
Questions
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Is this channel‑to‑channel decision‑level variation:
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A known hardware limitation?
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A firmware/software limitation?
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Something that can be corrected or calibrated?
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Is there:
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Any automatic calibration mechanism for decision levels across channels?
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A recommended best practice to achieve matched thresholds at high acquisition rates?
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Is there an elegant way to implement hysteresis on the decision level that could help mitigate this effect?
Current workaround (not ideal)
A possible workaround we are considering is feeding the same clock or toggling reference signal into multiple channels (e.g. A9, B9, C9, D9) and attempting to realign channels through post‑processing. However, this approach is neither clean nor robust and is far from ideal.
If needed, we can also provide .scana capture files and additional measurement details. Any clarification on whether this issue can be addressed—or must be accepted as a design limitation—would be extremely helpful.
Best regards,
Pedro Teixeira