SQ200 issue with SPI decoder @ 1V8 logic

[lucafach1]

Hi,

I’m trying to test communication on a 1V8 SPI bus, using the SPI decoder.

Unfortunatley, it seems something is wrong, because the signals are not acquired correctly (see the clock signal in the attached screensshot), i.e. at the beginning of transactions clock pulses are missing or irregular. Using a standard oscilloscope the signal appears good, instead. Are there any issue about using the 1.8V level on the sq200?

Thanks,

Luca Fachechi

[ikalogic]

Hello @lucafach1 ,

I’m not aware of any issue related to 1.8V on SQ devices.

What i find odd is the face that the clock tends to become valid after a few transactions.

Could you please share a longer capture, one were we can see several SPI transactions? i ‘ld like to know if the same phenomenon happends at the begining of each transaction.

Also, i assume you’ve double checked the GND connections?

[lucafach1]

Hi Ibrahim,

I attached the clock signal acquired with an oscilloscope and the data acquired during repeated SPI transactions.

The same issue happens at the beginning of each transaction.

The GND connection has been checked.

Luca

(Attachment test_spi.scana is missing)

(attachments)

[ikalogic]

Thanks.

Just to double check, you confirm this only happens with the 1.8V logic level?

[lucafach1]

Hi Ibrahim,

I didn’t tested at voltage level other than 1.8V, but I could.

I have 2 SQ200 and I could use one as generator while the other as logic analyzer.

Do you have an SPI pattern I could use for test ?

Luca

[ikalogic]

Interesting.

Well, you could simple generate a PWM with the right clock (a pattern PWM generator is already included in ScanaStudio normally).

I assume you see the exact same behavior with both SQ200 device?

[lucafach1]

Hi,

Yes, I see the same behavior on both the SQ200.

I generated the attached pattern, for both 1V8 and 2V8 test.

Luca

(attachments)

[lucafach1]

Here the result for 1V8.

The first clock are missing.

(attachments)

[lucafach1]

Instead for 2.8V clock seems ok.

I cannot perform tests for voltage levels in the middle.

Luca

(attachments)

[ikalogic]

Please allow us some time to further investigate this.

Your SPI clock is 1MHz, right?

In the mean time, we have sent you a private message with short term solutions, please let us know what you think.

[lucafach1]

Yes,

Clock is 1MHz.

Luca

[ikalogic]

I was able under some conditions to reproduce the issue.

I’ll need to further investigate this, but in the mean time, a simple workaround is the enable 10K internal pull-up resistors in ScanaStudio as in the image below:

This should fix the problem. Can you confirm?

[lucafach1]

I enabled mixed mode and 10K internal resistor on all channels, then I sampled at 100M SPS.

It works better, i.e. there are much less missing clock pulses, but sometime they still are.

(attachments)